A high-speed digital neural network chip with low-power chain-reaction architecture

Abstract

A high-speed digital neural network chip adopts a polyhedric discrimination neuron (PDN) model and low-power chain-reaction (LCR) architecture that can reduce the power dissipation to one-fiftieth or less. The chip contains 832 fully implemented digital synapse units that form 13 neurons on a 10.3-mm*14.1-mm die using 0.8- mu m CMOS technology. The synapse weights are updated using an external computer. A computational speed of 8 billion connections per second (GCPS) is achieved with low 54-mW power dissipation. The forward propagation time is 104 ns. These features make it possible to implement large-scale neural network chips and systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>