VLSI design of optimization and image processing cellular neural networks

Abstract

Detailed design of a current-mode cellular neural network for optimization and image processing is presented. The hardware annealing function is also embedded in the network. It is a paralleled version of fast mean-field annealing in analog networks, and is highly efficient in finding globally optimal solutions for cellular neural networks. The network was designed to perform programmable functions for fine-grained processing with annealing control to enhance the output quality. A 5/spl times/5 prototype chip was fabricated in a 2.0 /spl mu/m CMOS technology. Since the MOSIS scalable design rules are used, it is also suitable for submicron technologies. For high circuit reliability and compactness purpose, a unit current of 6.0 /spl mu/A is used. The cell density is 505 cell/cm/sup 2/ and the cell time constant is chosen to be 0.3 /spl mu/s. From this prototype, a scalable VLSI core of around 50/spl times/50 neural processors can be integrated on a 1-cm/sup 2/ silicon area in a 0.8 /spl mu/m technology. Experimental results of building blocks and the prototype chip are also presented.