IEEE Journal of Solid-State Circuits · 2002 · 37 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsCmos Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingDynamic Power ReductionLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignDirect Digital SynthesisDynamic RangeFrequency SynthesisFrequency SynthesizersLinear ApproximationLow-power SynthesisPortable Communication DevicesPower Consumption
A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values as in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a quadrature DDFS has been implemented using 0.5-/spl mu/m CMOS process and occupies an active area of 1.4 mm/sup 2/. It consumes 8 mW at 100 MHz and operates from a single 2.7-V supply. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz.
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