VeriTrust

TLDR

Hardware Trojans act as backdoors that can subvert device operation, causing functionality changes, data leaks, or denial‑of‑service attacks. This work introduces VeriTrust, a verification technique designed to detect hardware Trojans inserted during the design stage. VeriTrust automatically identifies potential Trojan trigger inputs by examining verification corners and remains insensitive to the Trojan’s implementation style. Experimental evaluation demonstrates that VeriTrust detects all tested Trojans from diverse design methodologies with only moderate additional verification time, outperforming existing solutions.

Abstract

Hardware Trojans (HTs) implemented by adversaries serve as backdoors to subvert or augment the normal operation of infected devices, which may lead to functionality changes, sensitive information leakages, or Denial of Service attacks. To tackle such threats, this paper proposes a novel verification technique for hardware trust, namely VeriTrust, which facilitates to detect HTs inserted at design stage. Based on the observation that HTs are usually activated by dedicated trigger inputs that are not sensitized with verification test cases, VeriTrust automatically identifies such potential HT trigger inputs by examining verification corners. The key difference between VeriTrust and existing HT detection techniques is that VeriTrust is insensitive to the implementation style of HTs. Experimental results show that VeriTrust is able to detect all HTs evaluated in this paper (constructed based on various HT design methodologies shown in the literature) at the cost of moderate extra verification time, which is not possible with existing solutions.