Preliminary description of Tabula Rasa, an electrically reconfigurable hardware engine

Abstract

Tabula Rasa is a user reconfigurable hardware system under development in AT&T Bell Labs. Its purpose is to assist in the development of new hardware systems, and possibly to serve as a computing engine in its own right. The core of the system is a full-custom CMOS chip. This chip has electrically programmed logic and routing, and allows an external monitor to observe, control, and reconfigure the circuit during operation. Unlike currently available programmable logic devices this chip is targeted specifically at the development rather than the production environment. One or more of these chips could be wired into the development version of an application system, to add flexibility and simplify the design process by making the design more controllable and observable. In another type of application, an array of these chips could be assembled into a dedicated processor attached to a workstation. The architecture of the chip, some of the tradeoffs involved, and the CAD challenges needed to support it are outlined.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>