An implementation algorithm and design of a novel leading zero detector circuit

Abstract

A novel way of implementing the leading zero detector (LZD) circuit is presented. The implementation is based on an algorithmic approach resulting in a modular and scalable circuit for any number of bits. This implementation is compared with the results obtained using modern logic synthesis (LS) tools in the same 0.9- mu m CMOS technology. This approach to LZD design yields both speed and area advantages over LS.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>