FPGA Implementation of LDPC Decoders Based on Joint Row-column Decoding Algorithm

Abstract

This paper presents a joint row-column decoding algorithm for the decoding of low-density parity-check (LDPC) codes. Simulation indicates that the proposed algorithm improves the performance in both the waterfall region and the error floor region. By combining row processing with column processing, the joint row-column decoding algorithm reduces the storage requirements of extrinsic messages and avoids memory conflicts and routing congestion during the exchanges of extrinsic messages. Implementation results into field programmable gate array (FPGA) devices indicate that the proposed algorithm reduces the hardware costs by 30% and increases the decoding speed by a factor of four. A 40-parallel decoder attains a throughput of 2 Gbits/sec by using up to 20 % of the generic logic resources in a Xilinx XC4LX160 device