A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control

Abstract

A 3rd-order hybrid (continuous-time and discrete-time) delta-sigma audio ADC, implemented in 65nm CMOS process, dissipates 15mW and occupies an active die area of 0.28mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A post integration time control (PITC) technique is proposed for calibration of the RC time constant variation of the continuous-time integrator. In addition, a jitter insensitive pulse generator (JIPG) circuit overcomes the degradation of SNR due to the feedback DAC clock jitter. The measured SNR and DR are 101dB and THD is −94dB.