Publication | Open Access
The Design of a Multicore Extension of the SPIN Model Checker
128
Citations
22
References
2007
Year
EngineeringHardware Verification LanguageVerificationMagnetic ResonanceComputer ArchitectureComputer-aided VerificationModel CheckingMemory Model (Programming)Multicore ExtensionSpin PhenomenonFormal VerificationHardware SecurityShared MemorySystems EngineeringParallel ComputingProper Load BalancingComputer EngineeringComputer ScienceSpin Model CheckerSpintronicsMany-core ArchitectureFormal MethodsParallel ProgrammingSpin Source Code
We describe an extension of the SPIN model checker for use on multicore shared-memory systems and report on its performance. We show how, with proper load balancing, the time requirements of a verification run can, in some cases, be reduced close to N-fold when N processing cores are used. We also analyze the types of verification problems for which multicore algorithms cannot provide relief. The extensions discussed here require only relatively small changes in the SPIN source code and are compatible with most existing verification modes such as partial order reduction, the verification of temporal logic formulas, bitstate hashing, and hash-compact compression.
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