A 9-Gbit/s Serial Transceiver for On-Chip Global Signaling Over Lossy Transmission Lines

Abstract

A 9-Gbit/s serial link transceiver for on-chip global signaling, and techniques for the design of on-chip transmission lines, are presented. In a prototype device, a transmitter serializes 8-b 1.125-Gbyte/s parallel data and transmits serial data over a 5.8-mm lossy on-chip transmission line. A receiver de-serializes the received data with the help of a digitally tuned interpolator. An on-chip lossy transmission line scheme is described. In the prototype, self-test circuitry verifies the recovered, de-serialized data against the original data and counts the number of discrepancies. The prototype transceiver, implemented in 0.13-mum 8-metal CMOS, achieves 9 Gbit/s with pre-defined data patterns.