Sensorless Digital Peak Current Controller for Low-Power DC-DC SMPS Based on a Bi-Directional Delay Line

Abstract

Peak current mode control is challenging to implement in integrated dc-dc converters for sub 1 W applications due to the need for an integrated high-bandwidth, low-noise current sensor. The analog sensor must typically consumes less than a few hundred micro-amps while amplifying the current through the high-side switch, which has frequency components extending into the ten's of MHz. Sensorless current mode control (SCM) eliminates the need for an explicit current sensor by reconstructing the inductor current from the system input/output voltages and the PWM signal pulse-width. In this work, a bidirectional delay line based digital SCM scheme is proposed. The inductor current is mapped onto the bi-directional delay line whose propagation delay tracks the inductor current slopes. An integrated digital current observer designed in a 0.18 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m CMOS process is compared to a benchmark analog current sensor operating at 2 MHz and fabricated in the same process. The digital current observer consumes 168 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> A, or 20% less then the benchmark at I <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">_out</i> = 100 mA, while avoiding signal-to-noise degradation at light loads. A prototype of the digital current sensor operating at 1 MHz is demonstrated on a CPLD platform.