IEEE Transactions on Power Electronics · 2008 · 86 citations · 15 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureField-programmable Gate ArraysReconfigurable ComputingClock ManagementDigital Signal ProcessingField-programmable Gate Array ArchitectureFpga ArchitectureLow-power Fpga DesignPulse-width ModulationDelay-locked LoopsDigital ModulationDigital Pulse-width ModulationDigital Signal Processing BlocksTime Resolution
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper proposes a new digital pulsewidth modulation (DPWM) architecture that takes advantage of the field-programmable gate array's (FPGA) advanced characteristics, especially the delay-locked loop (DLLs) present in almost every FPGA. The proposed DPWM combines a synchronous (counter-based) block with an asynchronous block for increased resolution without unnecessarily increasing the clock frequency. The experimental results show an implementation in a low-cost FPGA (Xilinx Spartan-3) that uses an external 32 MHz clock for a final time resolution under 2 ns. </para>
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