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Managing batch processors to reduce lead time in a semiconductor packaging line
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1997
Year
EngineeringIndustrial EngineeringComputer ArchitectureBatch ProcessorsOperations ResearchAdvanced Packaging (Semiconductors)Systems EngineeringLogisticsSensitivity AnalysisSemiconductor Packaging LineElectronic PackagingElectrical EngineeringLead TimeChip On BoardComputer EngineeringChip AttachmentIbm BromontSupply Chain ManagementMicroelectronicsProduction PlanningChip-scale PackageProduction SchedulingBusinessProduction Engineering
In this paper we study a semiconductor packaging line at IBM Bromont. At the line, modules are assembled and then tested in a burn-in oven. The burn-in oven is a batch processing station. We outline a procedure to determine order release schedule and lot sizes for the various work stations in the line, such that total manufacturing lead time is minimized. The internal parameters of the procedure are set by simulation experiments and by heuristics. Sensitivity analysis is carried out to determine the robustness of the procedure with respect to various external parameter settings.