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SMART: Secure and Minimal Architecture for (Establishing a Dynamic) Root of Trust
309
Citations
21
References
2012
Year
EngineeringInformation SecurityTrust Management ArchitectureComputer ArchitectureEmbedded SystemsHardware SystemsSoftware AnalysisFormal VerificationHardware SecurityRemote AttestationComputational TrustSystems EngineeringTrusted Execution EnvironmentSecure ComputingHardware Security SolutionHardware VerificationOperating System SecurityComputer EngineeringData PrivacyTrustComputer ScienceData SecurityCryptographyMinimal ArchitectureTrustworthy ComputingTrusted SystemOperating SystemsTrusted PlatformMcu SizeBlockchainSystem SoftwareSmart Implementations
Remote attestation is the process of securely verifying internal state of a remote hardware platform. It can be achieved either statically (at boot time) or dynamically, at run-time in order to establish a dynamic root of trust. The latter allows full isolation of a code region from preexisting software (including the operating system) and guarantees untampered execution of this code. Despite the untrusted state of the overall platform, a dynamic root of trust facilitates execution of critical code. Prior software-based techniques lack concrete security guarantees, while hardware-based approaches involve security co-processors that are too costly for low-end embedded devices. In this paper, we develop a new primitive (called SMART) based on hardware-software co-design. SMART is a simple, efficient and secure approach for establishing a dynamic root of trust in a remote embedded device. We focus on low-end microcontroller units (MCU) that lack specialized memory management or protection features. SMART requires minimal changes to existing MCUs (while providing concrete security guarantees) and assumes few restrictions on adversarial capabilities. We demonstrate both practicality and feasibility of SMART by implementing it – via hardware modifications – on two common MCU platforms: AVR and MSP430. Results show that SMART implementations require only a few changes to memory bus access logic. We also synthesize both implementations to an 180nm ASIC process to confirm its small impact on MCU size and overall cost.
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