A novel CVD-SiBCN Low-K spacer technology for high-speed applications

Abstract

State-of-the-art low-K spacer technology featuring novel CVD-SiBCN material is demonstrated for the first time. A significant 20% CMOS ring speed enhancement is demonstrated with SiBCN (K=5.2) spacer, compared to Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> (K=7.5) spacer, due to reduced fringing capacitance and enhanced strain effects by spacer-PSS and CESL techniques. Electron mobility is improved by 6% for long channel NMOS transistor and g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m,max</sub> is increased by 11% for short 35 nm physical gate length NMOS using a preferable spacer structure that is comprised of a low stress SiBCN spacer on thin SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> liner and a final 600degC rapid thermal post-anneal. Superior GIDL and better gate leakage is obtained because low permittivity SiBCN alleviates gate-fringing field effects (GF effects), and device reliability is not adversely impacted by this new process.