Modeling and experimental verification of high impedance arcing fault in medium voltage networks

Abstract

A high impedance arcing fault due to a leaning tree in medium voltage (MV) networks is modeled and experimentally verified. The fault is represented in two parts; an arc model and a high resistance. The arc is generated by a leaning tree towards the network conductor and the tree resistance limits the fault current. The arcing element is dynamically simulated using thermal equations. The arc model parameters and resistance values are determined using the experimental results. The fault behavior is simulated by the ATP/EMTP program, in which the arc model is realized using the universal arc representation. The experimental results have validated the system transient model. Discrete wavelet transform is used to extract the fault features and therefore localize the fault events. It is found that arc reignitions enhance fault detection when discrete wavelet transform is utilized