Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 $\mu$m HV-CMOS Technology

Abstract

We present novel circuits for high-voltage digital level shifting with zero static power consumption. The conventional topology is analysed, showing the strong dependence of speed and dynamic power on circuit area. Novel techniques are shown to circumvent this and speed up the operation of the conventional level-shifter architecture by a factor of 5-10 typically and 30-190 in the worst case. In addition, these circuits use 50% less silicon area and exhibit a factor of 20-80 lower dynamic power consumption typically. Design guidelines and equations are given to make the design robust over process corners, ensuring good production yield. The circuits were fabricated in a 0.35 high-voltage CMOS process and verified. Due to power and IO speed limitation on the test chip, a special ring oscillator and divider structure was used to measure inherent circuit speed.