A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOS

Abstract

A divide-by-4 circuit operates for input frequencies from 31 to 41 GHz at signal amplitudes "0.5V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> . The circuit consists of a dynamic followed by a static frequency divider. The dynamic and static frequency dividers consume 2mA and 1mA, respectively, from a 1.1V supply