A zero-crossing based 12b 100MS/s pipelined ADC with decision boundary gap estimation calibration

Abstract

This paper describes a 12-bit zero-crossing based pipeline 100-MS/s ADC. The prototype ADC, fabricated in a 90-nm CMOS process, occupies 0.32 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The capacitor mismatch is calibrated by decision boundary gap estimate algorithm that runs in the background. It achieves an ENOB of 10.2 bits for a 49 MHz input signal and dissipates 6.2 mW from a 1.2V supply for a FOM of 53fJ/step.