EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysReconfigurable ComputingDigital Image ProcessingDigital Integrated CircuitsDigital Signal ProcessingField-programmable Gate Array ArchitectureFpga ArchitectureImage ProcessingDigital Signal Processing Block ArchitectureDigital Signal Processing BlocksMultiplier DesignOn-chip Memory DesignOn-chip Memory Hierarchies
This paper presents an evaluation of an algorithm for performing the forward and inverse discrete cosine transforms (DCT) on digital images using a hybrid-logarithmic number system (hybrid-LNS) instead of linear binary arithmetic. The algorithm has been simulated using Matlab/sup /spl reg// where the accuracy of the fractional part of the logarithm has been limited to 8 bits and has been calculated using just 4, 6 or 8 binary address bits of the linear input data. The results show that it is possible to use this hybrid-LNS architecture to build multiplierless DCT and IDCT transforms having only a minimal reduction in image quality. The algorithm is suitable for implementation on existing mid-range FPGA technologies where there are limitations on the size of on-chip memory and high-speed computing elements.
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Arithmetic on the European logarithmic microprocessor
J.N. Coleman, Ed Chester, C.I. Softley et al. · IEEE Transactions on Computers · 2000 · 134 citations