Micro-operation cache

Abstract

Article Share on Micro-operation cache: a power aware frontend for the variable instruction length ISA Authors: Baruch Solomon Intel Corporation, Intel Israel (74) Ltd., P.O. Box 1659, Haifa 31015, Israel Intel Corporation, Intel Israel (74) Ltd., P.O. Box 1659, Haifa 31015, IsraelView Profile , Avi Mendelson Intel Corporation, Intel Israel (74) Ltd., P.O. Box 1659, Haifa 31015, Israel Intel Corporation, Intel Israel (74) Ltd., P.O. Box 1659, Haifa 31015, IsraelView Profile , Doron Orenstein Intel Corporation, Intel Israel (74) Ltd., P.O. Box 1659, Haifa 31015, Israel Intel Corporation, Intel Israel (74) Ltd., P.O. Box 1659, Haifa 31015, IsraelView Profile , Yoav Almog Intel Corporation, Intel Israel (74) Ltd., P.O. Box 1659, Haifa 31015, Israel Intel Corporation, Intel Israel (74) Ltd., P.O. Box 1659, Haifa 31015, IsraelView Profile , Ronny Ronen Intel Corporation, Intel Israel (74) Ltd., P.O. Box 1659, Haifa 31015, Israel Intel Corporation, Intel Israel (74) Ltd., P.O. Box 1659, Haifa 31015, IsraelView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 4–9https://doi.org/10.1145/383082.383085Published:06 August 2001Publication History 22citation475DownloadsMetricsTotal Citations22Total Downloads475Last 12 Months85Last 6 weeks22 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access