Multi-Rate High-Throughput LDPC Decoder: Tradeoff Analysis Between Decoding Throughput and Area

Abstract

In order to achieve high decoding throughput (hundreds of MBits/sec and above) for multiple code rates and moderate codeword lengths, several LDPC decoder solutions with different levels of processing parallelism are possible. Selection between these solutions is based on a threefold criterion: hardware complexity, decoding throughput, and error-correcting performance. In this work, we determine the multi-rate LDPC decoder architecture with the best tradeoff in terms of area cost, error-correcting performance, and decoding throughput. The prototype architecture of this decoder is implemented on an FPGA