Digital Enhanced V$^{2}$-Type Constant On-Time Control Using Inductor Current Ramp Estimation for a Buck Converter With Low-ESR Capacitors

Abstract

This paper proposes a new digital enhanced V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> -type constant on-time control architecture for solving the ripple oscillation issues when using low-equivalent series resistance (ESR) capacitors in a buck converter. Instead of directly sensing the inductor current, an inductor current ramp estimator with the drift compensation is presented as adding a virtual ESR ripple to the output voltage. Only the input and output voltages are required to be sampled with analog-to-digital converters (ADCs) for estimating the inductor current ramp. Since the sampling rate and resolution requirements of ADCs for voltage sensing are usually less critical with compared to direct current sensing, the proposed digital control architecture is practical for low-cost applications. Besides, the limit-cycle oscillations due to the sampling effects can also be improved by using the estimated current ramp. Furthermore, the small-signal model of the proposed digital enhanced V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> control architecture is provided to design the estimated current ramp amplitude to stabilize the system and to optimize the system performance. The drift compensation effect is also analyzed in this paper. The effectiveness of the proposed control architecture with the current ramp estimator has been verified with simulation and experimental results by using an FPGA-based hardware platform.