2010 · 19 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital Converter DesignAnalog-to-digital ConvertersComparator DesignComparatorsPower Supply RejectionPower Supply Rejection Ratio
This paper proposes 4-bit, 1.8V Flash Analog to Digital Converter (ADC) design using CMOS-LTE (CMOS Linear Tunable Transconductance Element) Comparator with 500nm technology. Reference voltages are generated by systematically sizing the transistors of the comparators, thus completely eliminating the resistive ladder network required for the architecture. The PSRR (Power Supply Rejection Ratio) results obtained are compared with 4-bit TIQ (Threshold Inverter Quantizer) Comparator Flash Analog to Digital Converter designed with 500nm technology. It is observed that, with the use of CMOS-LTE Comparator PSRR is improved. The DC simulation results of CMOS-LTE Comparator ADC shows DNL and INL of +0.16/-0.16 LSB and +0.16/-0.104 LSB. The total power dissipation observed is 0.28753 mW.
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