A Q-Band Amplifier Implemented with Stacked 45-nm CMOS FETs

Abstract

A stacked FET, single-stage 45-GHz (Q-band) CMOS power amplifier (PA) is presented. The design stacked three FETs to avoid breakdown while allowing a high supply voltage. The IC was implemented in a 45-nm CMOS SOI process. The saturated output power exceeds 18 dBm from a 4-V supply. Integrated shielded coplanar waveguide (CPW) transmission lines as well as metal finger capacitors were used for input and output matching. The amplifier occupies an area of 450×500 im <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including pads, while achieving a maximum power-added-efficiency (PAE) above 20%.