Characterization and elimination of trench dislocations

Abstract

Trench dislocations in a 0.25 μm BiCMOS SRAM technology were traced to defects arising during S/D processing. It is argued that these defects coalesce to form dislocations, typically near the trench edge, under the combined influence of mechanical stress and high temperature processing. Process variables impacting the generation of these dislocations, including layout geometry; trench depth, profile, and densification; the presence of a liner under the gate spacer nitride; and S/D implant condition and anneal are studied. Based on this analysis, a defect-free BiCMOS process is proposed. It is shown that although the incidence of trench dislocations could be decreased by reducing the overall stress in the flow, eliminating S/D implant defects is the key to completely removing the trench dislocations.