Power LDMOS with novel STI profile for improved Rsp, BVdss, and reliability

Abstract

The profile of shallow trench isolation (STI) is designed to improve LDMOS specific on-resistance (Rsp), BVDSS, safe operating area (SOA), and hot carrier lifetimes (HCL) in an integrated BiCMOS power technology. Silicon etch, liner oxidation and CMP processes are tuned to improve the tradeoffs in a power technology showing significant improvement to both p-channel and n-channel Rsp compared to devices fabricated with the STI profile inherited from the original submicron CMOS platform. Extensive TCAD and experiments were carried out to gain insight into the physical mechanisms and further improve device performance after STI process optimization. The final process and device structures yield SOAs that are limited only by thermal constraints up to rated voltages