2005 · 59 citations · 12 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureMicroelectronicsSystem-on-chip DesignCmos Circuit DesignCryptographic AlgorithmsCryptographic ImplementationMicroarchitecture DesignProcessor Core DesignProcessor MicroarchitectureCryptographic Accelerator DesignCryptographic AcceleratorsCryptographic OperationsHardware Acceleration For CryptographyMemory-mapped OutputSecure Embedded System DesignSecurity HardwareThroughput
In this paper an AES crypto coprocessor that is fabricated using a 0.18-μm CMOS technology is presented. This crypto coprocessor performs the AES-128 encryption in both feedback and non-feedback modes of operation. A maximum throughput of 3.84 Gbits/s is achieved at a 330 MHz clock frequency for ECB, OFB, and CBC modes of operation. This crypto coprocessor can be programmed using the memory-mapped interface of an embedded CPU core and is tested using a LEON 32-bit (SPARC V8) processor in the ThumbPod secure system-on-chip.
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A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
A. Hodjat, Ingrid Verbauwhede · 2004 · 219 citations