A Sub-μs wake-up time power gating technique with bypass power line for rush current support

Abstract

A sub-mus wake-up power gating technique was developed for low power SOCs. It uses two types of power switches and separated power lines bypassing rush current to suppress power supply voltage fluctuations. We applied this technique to a heterogeneous dual-core microprocessor fabricated in 90 nm CMOS technology. When wake-up time on the 2M-gate scale circuit was set to 0.24 mus, the supply voltage fluctuation was suppressed to 2.5 mV.