Identification and authentication of integrated circuits

TLDR

The paper proposes a technique to reliably and securely identify individual integrated circuits by precisely measuring circuit delays and using a simple challenge–response protocol. The method involves precise delay measurement and a challenge–response protocol, and the authors evaluate potential attack vectors and propose candidate implementations. Experiments on FPGAs demonstrate the technique is viable, enabling more secure key‑cards than digital‑key ICs, though current implementations need strengthening for full security. © 2004 John Wiley & Sons, Ltd.

Abstract

Abstract This paper describes a technique to reliably and securely identify individual integrated circuits (ICs) based on the precise measurement of circuit delays and a simple challenge–response protocol. This technique could be used to produce key‐cards that are more difficult to clone than ones involving digital keys on the IC. We consider potential venues of attack against our system, and present candidate implementations. Experiments on Field Programmable Gate Arrays show that the technique is viable, but that our current implementations could require some strengthening before it can be considered as secure. Copyright © 2004 John Wiley & Sons, Ltd.