A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth

Abstract

This paper presents a sixth-order bandpass ΣΔ modulator with 10 MHz bandwidth and 200 MHz center frequency suitable for high-IF applications. The <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fs</i> /4 modulator employs an 800 MHz clock frequency and uses an active <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> loop filter implemented with three-stage linearized operational amplifiers achieving more than 50 dB gain at 200 MHz. Furthermore, a calibration technique is proposed to compensate for process-voltage-temperature (PVT) variations, which involves measurement and optimization of the noise transfer function by injecting two auxiliary tones at the quantizer input. The modulator achieves 68.4 dB peak SNDR measured in 10 MHz bandwidth and IM3 of -73.5 dB at -2 dBr input signal. Fabricated in a vanilla 0.18 μm CMOS technology, the modulator consumes 160 mW (static + dynamic power) and occupies an active silicon area of 2.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .