Architecture of a Single-Chip 50 Gb/s DP-QPSK/BPSK Transceiver With Electronic Dispersion Compensation for Coherent Optical Channels

Abstract

The architecture of a single-chip dual-polarization QPSK/BPSK 50 Gigabits per second (Gb/s) DSP-based transceiver for coherent optical communications is presented. The receiver compensates the chromatic dispersion (CD) of more than 3,500 km of standard single-mode fiber using a frequency-domain equalizer. A time-domain four-dimensional MIMO transversal equalizer compensates up to 200 ps of differential group delay (DGD) and 8000 ps <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of second-order polarization-mode dispersion (SOPMD). Other key DSP functions of the receiver include carrier and timing recovery, automatic gain control, channel diagnostics, etc. A novel low-latency parallel-processing carrier recovery implementation which is robust in the presence of laser phase noise and frequency jitter is proposed. The chip integrates the transmitter, receiver, framer and host interface functions and features a 4-channel 25 Gs/s 6-bit ADC with a figure of merit (FOM) of 0.4 pJ/conversion. Each ADC channel is based on an 8-way interleaved flash architecture. The DSP uses a 16-way parallel processing architecture. Extensive measurement results are presented which confirm the design targets. Measured optical signal-to-noise ratio (OSNR) penalty when compensating 200 ps DGD and 8000 ps <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is 0.1 dB, while OSNR penalty when compensating 55 ns/nm CD (corresponding to 3,500 km of standard single-mode fiber) is 0.5 dB.