Pipelined, time-sharing access technique for an integrated multiport memory

Abstract

A pipelined, time-sharing access (PTA) technique that realizes an integrated multiport memory for high-speed signal processing is described. N/2-port memory cells, with less area and a wider operating margin, are used for the N-port memory function. Memory cell access for multiple ports is performed serially within one cycle, instead of being an ordinary parallel operation. Memory operation is divided into three pipeline cycles-address selection, memory cell access, and data I/O operation-to reduce the cycle time. A 64-kb four-port memory was fabricated with conventional two-port memory cells to verify the effectiveness of this technique. A 16 ns memory operation with a wide margin was observed under a 3 V supply voltage.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>