A digital design flow for secure integrated circuits

TLDR

Small embedded ICs such as smart cards are vulnerable to side‑channel attacks that exploit power consumption, execution time, electromagnetic radiation, and other leakage from digital CMOS gates. This paper proposes a digital VLSI design flow that produces power‑analysis‑attack‑resistant integrated circuits. The flow begins with a normal HDL design, modifies library databases to implement dynamic, differential logic, adjusts synthesis, placement, and routing constraints, and enables routing of over 20 000 differential nets without a full custom layout. Experimental measurements demonstrate that the flow effectively thwarts side‑channel power analysis, protecting a prototype AES IC fabricated in 0.18‑µm CMOS.

Abstract

Small embedded integrated circuits (ICs) such as smart cards are vulnerable to the so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power consumption, execution time, electromagnetic radiation, and other information leaked by the switching behavior of digital complementary metal-oxide-semiconductor (CMOS) gates. This paper presents a digital very large scale integrated (VLSI) design flow to create secure power-analysis-attack-resistant ICs. The design flow starts from a normal design in a hardware description language such as very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) or Verilog and provides a direct path to an SCA-resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. The basis for power analysis attack resistance is discussed. This paper describes how to adjust the library databases such that the regular single-ended static CMOS standard cells implement a dynamic and differential logic style and such that 20 000+ differential nets can be routed in parallel. This paper also explains how to modify the constraints and rules files for the synthesis, place, and differential route procedures. Measurement-based experimental results have demonstrated that the secure digital design flow is a functional technique to thwart side-channel power analysis. It successfully protects a prototype Advanced Encryption Standard (AES) IC fabricated in an 0.18-mum CMOS