An area-efficient PLL architecture in 90-nm CMOS

Abstract

An area-efficient phase-locked loop (PLL) design is presented. The PLL architecture allows the implementation of a charge-pump based PLL stabilization filter network using sample-reset techniques and a total loop-capacitor equivalent to a typical ripple-reduction capacitor. Implemented in a logic 90-nm CMOS process, this PLL integrates a total loop capacitance of 3 pF using parasitic metal-metal capacitor structures, measures 160 /spl times/ 171 /spl mu/m and exhibits a measured rms period jitter of 1.68 ps at 2.5 GHz.