A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector

Abstract

A 12 bit 160 MS/s two-step pipelined SAR ADC was fabricated in a 40 nm CMOS low-leakage digital process. A background bit-weight calibration exploiting the comparator resolving time information and the employment of a sub-binary DAC in the first SAR stage are two key techniques in this work to attain high conversion throughput and power savings at the same time using a simple, low-gain (~30 dB) residue amplifier. The overall architecture and the digital calibration also enable the downsizing of the first SAR stage to that of the kT/C limit, yielding a wideband input network delivering an over 80 dB spurious-free dynamic range (SFDR) while digitizing a 300 MHz input at 160 MS/s. The core ADC consumes 4.96 mW and occupies an area of 0.042 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ; the calibration circuits dissipate 0.1 mW (estimated). An 86.9 dB SFDR and a 66.7 dB signal-to-noise plus distortion ratio (SNDR) were measured with a 2 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> , 5 MHz sine-wave input at full speed. The ADC achieves a Walden figure-of-merit (FoM) of 20.7 fJ/conversion-step with a Nyquist input.