A 60GHz digitally controlled phase shifter in CMOS

Abstract

This paper presents a 60 GHz digitally controlled phase shifter in the 65 nm CMOS technology. Using a differential varactor-loaded transmission-line architecture, the phase shifter achieves a phase resolution of 22.5deg, an average insertion loss of 8.5 to 10.3 dB and a return loss of better than 10 dB from 55 to 65 GHz. The phase shifter occupies an area of only 0.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To the knowledge of the authors, this is the first 60 GHz digitally controlled phase shifter with a phase resolution of 22.5deg in silicon reported to date. It is well suited for a 60 GHz phased array.