Register window management for a real-time multitasking RISC

Abstract

An architecture is proposed that allows fast procedure calls, low-overhead task switches, and primitives, which assist in queue-oriented intertask communications. This is accomplished by managing the registers as noncontiguous register windows. The details of the register granularity are hidden from the applications program. The architecture is based on a VLSI CPU called the MULTIS, which is capable of handling the dynamically created data of multiple tasks in on-chip storage. This ability enables tasking systems to benefit from the use of large on-chip memories such as those found in RISC (reduced-instruction-set computer) technologies. Other features of the architecture include efficient interrupt handling and provision for register-based task local, procedure-global dynamic storage.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>