Hybrid CMOS and CNFET Power Gating in Ultralow Voltage Design

Abstract

This paper proposes a new hybrid MOSFET/carbon nanotube FET (CNFET) power-gating (PG) method using 32 nm technology in the ultralow-voltage region (~0.4 V). Traditionally, PG is one of the most effective methods to reduce the power dissipation of systems in sleep mode, but it suffers from increased propagation delay and wake-up time due to the high-threshold voltage of power switches in the low-voltage region. In this paper, to reduce the propagation delay and wake-up time of the PG structure while keeping low leakage power in the sleep mode, the CNFET power switches are combined with silicon MOSFET logic cells. The proposed hybrid structure reduces the time gap in switching over from silicon MOSFET to CNFET technology. For the tradeoff between wake-up overhead and leakage power saving, a new four-power-mode PG structure and a new two-pass PG structure using back-gate biasing of the CNFET switches are used. The simulation results of the proposed hybrid PG at 0.4 V are compared with those of the logic blocks without PG and the MOSFET PG structure using low-threshold voltage power switches. The simulation results show that the proposed hybrid structure reduces the total leakage power by 69.07%, the rush current by 5.13%, and the delay by 5.96%, on average, compared to the conventional PG structure for ISCAS85 benchmark circuits designed in 32 nm technology. More specifically, the proposed structure reduces the total leakage by 95.85% at the cost of 3% delay penalty compared to the logic blocks without PG for ISCAS85 benchmark circuits designed in 32 nm technology.