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A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance
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2012
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Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignPower IcMixed-signal Integrated CircuitComputer EngineeringFabricated ChipDigital Circuit DesignPower ElectronicsMicroelectronicsHybrid OperationPower-aware DesignPll-modulated Switching RegulatorTimes Mips Performance
A 50nA quiescent current asynchronous digital-LDO (DLDO) integrated with the PLL-modulated switching regulator (SWR) exhibits the hybrid power management operation. The proposed bidirectional asynchronous wave pipeline (BAWP) in the asynchronous DLDO realizes the Fast-DVS (F-DVS) operation within tens of nano-seconds. The SWR with the leading phase amplifier achieves on-the-fly DVS and 94% peak efficiency, as well as improves 5.6 times MIPS performance through hybrid operation. The fabricated chip occupies 1.04mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 40nm CMOS.