Compression of FPGA bitstreams using improved RLE algorithm

Abstract

FPGA are configured using bit streams often loaded from memory. FPGA often called as reconfigurable design because it lower the memory requirements, reduce the bitstreamsize. Some techniques are not suitable for real time decompression. There is need to design a compression technique which efficiently reduces bit stream size meanwhile keeping decompression ratio minimum. In our technique there are some major part of work which are more important they are 1) smart arrangements of the compressed bits that can significantly decreases the overhead of decompression engine 2) combination of bitmask-based compression and run length encoding of repetitive patterns 3)selection of profitable parameter for bit stream compression. The proposed techniques outperforms the compression ratio of existing techniques by 5-15% and decompression hardware is capable of operating at 200M H Z.