A digitally controlled 5GHz analog phase interpolator with 10GHz LC PLL

Abstract

This paper describes a 5GHz Analog Phase Interpolator (API) for clock synthesis and clock data recovery dedicated to multi-gigabit/s serial link applications. The system includes a 10GHz LC Phase Locked Loop for clock generation and an Analog Phase Interpolator implemented with Current Mode Logic (CML) offering better phase noise and speed performances compared to CMOS logic. It has been implemented in ST’s 65nm RfCMOS technology. The core of the API occupies a silicon area of 0.09x 0.17mm2 and dissipates less than 22.56mW from a 1.2V voltage supply.