IEEE Journal of Solid-State Circuits · 1997 · 42 citations · 13 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsSystem-on-chip DesignAnalog Integrated CircuitsClock ManagementCmos Circuit DesignDynamic Power ReductionLow-noise Circuit DesignMixed-signal Integrated Circuit DesignBicmos TechnologyClock JitterClock RecoveryCmos Analog Circuit DesignCmos Analog Integrated CircuitsEqualizationEqualization In RecordingSettling Time
This paper presents a 160-MHz five-tap adaptive analog equalizer for magnetic recording disk drive read channels. The design is based on a direct form finite impulse response (FIR) architecture which includes four key features: signal shuffling in the analog domain to improve noise performance, use of a master sample-and-hold stage to improve the dynamic performance and clock jitter of the clock recovery loop, use of an additional sample-and-hold stage to accommodate settling time requirements and reduce power, and use of a time interleaved sign-sign LMS algorithm which permits coefficient adaptation at low power and area. This equalizer occupies 1.36 mm/sup 2/ and consumes only 240 mW with 5-V supply voltage. It is fabricated in BiCMOS technology with 0.8-/spl mu/m CMOS and 0.72-/spl mu/m/sup 2/ NPN, 3LM, and DP capacitor.
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