A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction

Abstract

With reducing feature size of transistors and increasing number of cores on a single chip, fault tolerance and reliability have become two significant challenges for IC designers. Since chip design is extremely cost-sensitive, the fault tolerance redundancy must be provided at a reasonable cost. In this paper, a fault tolerant NoC architecture with cores linked to two switches instead of one, is proposed. This architecture is able to save cores with a faulty switch. Also, to be more efficient and to compensate this redundancy, a new routing algorithm is suggested that can be dynamically reconfigured to escape faulty switches. According to evaluation of the proposed architecture, latency and reliability are improved.