An analog PLL-based clock and data recovery circuit with high input jitter tolerance

Abstract

A clock and data recovery circuit for a T1 network is described. A fully integrated phase-locked loop (PLL) extracts the carrier signal embedded in the data. Two trimming DACs simultaneously bring the VCO center frequency and the PLL closed-loop bandwidth to their specified values. A triple sampler captures the jittering data and aligns them with the recovered clock. The input jitter of this circuit is three times more than previously reported PLL-based circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>