Delay and power expressions characterizing a CMOS inverter driving an RLC load

Abstract

On-chip parasitic inductance has become an important design issue in high speed integrated circuits. On-chip inductance may degrade on-chip signal quality, affect transmission delay, and cause additional short-circuit power dissipation. The effects of on-chip inductance on the output voltage, propagation delay, and short-circuit power of a CMOS inverter are presented in this paper. Analytic equations characterizing the output voltage are derived based on an assumption of a fast ramp input signal. Closed form expressions describing the short-circuit power are also presented, The accuracy of these analytic equations is within 10% as compared to SPICE simulations. It is demonstrated that large inductive loads and fast input transition times can increase short-circuit current.