Active pages: a computation model for intelligent memory

TLDR

Microprocessors and memory systems suffer from a growing gap in performance. The authors introduce Active Pages, a computation model that shifts data‑intensive computations to the memory system to close this gap. Active Pages are implemented as a data page coupled with executable functions, deployed on RADram—a DRAM–reconfigurable logic system—and evaluated for sensitivity across other memory technologies. Simulations show up to a 1000‑fold speedup for several applications on RADram compared to conventional memory systems.

Abstract

Microprocessors and memory systems suffer from a growing gap in performance. We introduce Active Pages, a computation model which addresses this gap by shifting data-intensive computations to the memory system. An Active Page consists of a page of data and a set of associated functions which can operate upon that data. We describe an implementation of Active Pages on RADram (Reconfigurable Architecture DRAM), a memory system based upon the integration of DRAM and reconfigurable logic. Results from the SimpleScalar simulator [BA97] demonstrate up to 1000X speedups on several applications using the RADram system versus conventional memory systems. We also explore the sensitivity of our results to implementations in other memory technologies.