An area estimation methodology for FPGA based designs at systemc-level

Abstract

This paper presents a parametric area estimation methodology at SystemC level for FPGA-based designs. The approach is conceived to reduce the effort to adapt the area estimators to the evolutions of the EDA design environments. It consists in identifying the subset of measures that can be derived form the system level description and that are also relevant at VHDL-RT level. Estimators ’ parameters are then automatically derived from a set of benchmarks.