Device mismatch and tradeoffs in the design of analog circuits

TLDR

Random device mismatch significantly affects accurate analog circuit design, and literature models show that MOS and bipolar device matching improves with increasing device area. The paper investigates how the minimal device area required by accuracy constraints affects the performance of general analog circuits. The study compares matching‑imposed performance limits to thermal‑noise limits and briefly examines how technology scaling influences these conclusions. The analysis shows a fixed bandwidth‑accuracy‑power tradeoff governed by technology constants; for bipolar circuits this tradeoff is bias‑point independent, while MOS circuits allow bias optimizations, and power constraints from matching are orders of magnitude higher than thermal noise in MOS but comparable to noise in bipolar.

Abstract

Random device mismatch plays an important role in the design of accurate analog circuits. Models for the matching of MOS and bipolar devices from open literature show that matching improves with increasing device area. As a result, accuracy requirements impose a minimal device area and this paper explores the impact of this constraint on the performance of general analog circuits. It results in a fixed bandwidth-accuracy-power tradeoff which is set by technology constants. This tradeoff is independent of bias point for bipolar circuits whereas for MOS circuits some bias point optimizations are possible. The performance limitations imposed by matching are compared to the limits imposed by thermal noise. For MOS circuits the power constraints due to matching are several orders of magnitude higher than for thermal noise. For the bipolar case the constraints due to noise and matching are of comparable order of magnitude. The impact of technology scaling on the conclusions of this work are briefly explored.