FPGA implementation of MD5 hash algorithm

Abstract

In information security, message authentication is an essential technique to verify that received messages come from the alleged source and have not been altered. A key element of authentication schemes is the use of a message authentication code (MAC). One technique to produce a MAC is based on using a hash function and is referred to as an HMAC. The Message Digest 5 (MD5) is one of the algorithms, which has been specified for use in Internet Protocol Security (IPSEC), as the basis for an HMAC. The input message may be arbitrarily large and is processed in 512-bit blocks by executing 64 steps involving the manipulation of 128-bit blocks. There is an increasing interest in high-speed cryptographic accelerators for IPSEC applications such as virtual private networks. As we show, it is reasonable to construct cryptographic accelerators using hardware implementations of HMACs based on a hash algorithm such as MD5. Two different architectures, iterative and full loop unrolling, of MD5 have been implemented using field programmable gate arrays (FPGAs). The performance of these implementations is discussed.